The present invention relates to a data processor comprising a register file and a plurality of operational units.
With recent advances in LSI technology, a high-performance digital signal processor has been implemented on a single chip to perform complicated data processing including addition, subtraction, and multiplication. In such a field of application as mobile telephone, high-speed data processing is particularly needed to perform compression/decompression of a large amount of information.
A known example of a high-speed data processor uses a pipeline control system, which comprises a small-capacity and high-speed register file in addition to a large-capacity memory such as a SRAM (static random access memory) and a low-speed memory such as a ROM (read-only memory). The pipeline data processor is composed of the register file having a plurality of general-purpose registers each for storing data and a plurality of operational units including an arithmetic and logic unit and a multiplier unit, which are connected to each other via buses. In the pipeline data processor, the high-speed register file is used to store data for operation. For example, the arithmetic and logic unit receives two operands from the register file and performs the addition of the two operands in response to an addition instruction. Data representing the result of the addition is written in a designated one of the general-purpose registers in the resister file. The multiplier unit receives two operands from the register file and performs the multiplication of the two operands in response to a multiplication instruction. Data representing the result of the multiplication is written in a designated one of the general-purpose registers in the register file.
In general, a multiplication process requires a longer time than an addition/subtraction process. Therefore, the multiplier unit forms a critical path in a conventional pipeline data processor so that the upper-limit frequency of a pipeline clock is determined by the multiplier unit. Besides, the time required to write the result of the operation performed by the multiplier unit in the register file via a bus is not negligible because it causes a serious delay in data transfer via the bus forming a long path.